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Senior systems design engineer – fec

Infinera

This is a Full-time position in Ottawa, ON posted January 14, 2020.

Infinera is seeking a person experienced, with a track record in designing algorithms for soft decoding FEC that can approach channel capacity.The candidate will be part of a DSP algorithm design team.

The application is a high throughput, 10% to 50% OH, and for use in fiber optic communication systems at greater than 100Gbit/sec data rates.

Must have working knowledge in the following areas:Binary BCH codes, Reed Solomon codesTurbo Product codes based on component binary BCH codesBinary LDPC codes, regular, irregular, spatially coupledStaircase codes, 400G ZR FECEducation and ExperiencePh.D.5+ years of experience as indicated in the following areas:Must have done previous Matlab/C coding in some of these FEC schemes.

ASIC and FPGA design experience is not required.

However, it is relevant and valuable to have an understanding of ASIC implementation, parallelism, high throughput implementation, fixed point arithmetic, performance tradeoffs, and have a general understanding in critical timing closure issues in ASIC design.Must have great inter-personal working styles, and strong independent work ethic, and good communication skillsInfinera is an equal opportunity employer.

All qualified applicants will receive consideration for employment without regard to race, religion, color, national origin, sex, age, status as a protected veteran, or status as a qualified individual with disability.

EEO Employer/Vet/Disabled.